Implementation of a Programmable High Speed Divider for a 2.4 Ghz Cmos Integer-n Frequency Synthesizer

The implementation of a programmable high speed divider for a CMOS Frequency Synthesizer, using 0.35 μm CMOS technology, is described. The Frequency Synthesizer is part of a RF transceiver to work in the 2.4 GHz ISM (Industrial, Scientific and Medicine) band. The programmable divider employs: a divide-by-32/33 dual-modulus prescaler composed by a divide-by-4/5 synchronous counter, using the Extended True Single Phase Clock (E-TSPC) technique, and a divide-by-8 asynchronous counter; two other counters, a fixed and a descending programmable (swallow) counter; and the necessary control logic to operate the divider. Additionally, a complete Synthesizer was fully designed to test the divider; it includes a VCO, a phase frequency detector with charge pump, a low pass filter, buffers to increase the signal levels, and the programmable divider itself. The results obtained by means of layout simulations show a maximum frequency of 2.75 GHz and power consumption of 5.6 mW with 3.3V power supply. The programmable divider has 198 μm x 33 μm and the prescaler has 77 μm x 33 μm.